FAQ: ADL5902 RMS Detector Output Voltage Clamping for High Input Power Levels

Document created by enash Employee on Apr 22, 2010Last modified by AndyR on Jan 31, 2012
Version 2Show Document
  • View in full screen mode


At high input power levels (above 0 dBm), the output voltage of the ADL5902 rms detectors (and some other rms detectors also) loses linearity and clamps to the rail. What causes this and is there any way to prevent it?




The plot below illustrates the effect you are describing. In this case, as the input power approaches +3 dBm,  the output voltage starts increasing rapidly and clamps at a level of around 4.7 V (this clamping  level varies with temperature).

ADL5902 Vout vs Pin at 2140 MHz.JPG

This effect is caused by the internal architecture of the ADL5902.  In its normal operating mode, Vout connects to Vset. This closes an internal AGC loop which uses a VGA to present a constant input level to the internal square law detector (one of the X2 blocks).  As the input level increases, the gain control voltage to the detector (which is also the final output voltage), keeps increasing which causes the gain of the VGA to decrease. When the gain cannot be decreased any further, the AGC loop's integrator voltage (Vout) goes open loop and clamps to the rail (approx 4.7V).


ADL5902 Block Diagram.JPG


If you do not want the device to behave in this manner, the most practical solution is to increase the slope of the transfer function by connecting a resistor divider between Vout, Vset and ground (as described in the datasheet). This will give higher Vout voltages for a particular input power. So you could set the slope so that the output voltage is equal to 4.6 V for an input level of +3 dBm. If you increase the input level above +3dBm the loop will still open up but the output voltage jump will be much smaller. In this example, the voltage will jump from 4.6 V to approx 4.7V (clamp level varies with temperature).