QAD9517-1 delay to output of channel divider: When I look at figure 57 "SYNC
Timing When VCO Divider Is Used—CLK or VCO Is Input"(datasheet rev D) (that is
how we are using our design now), it takes 14 to 15 cycles at the channel
divider input + 1 cycle at the vco divider input in order to output a clock.
The VCO is running @ 2.56 GHz and I would like to have 10 MHz output clocks, I
am dividing the VCO by 4 (generating 640 MHz) and the first channel divider by
32 (generating 20 MHz) and the second channel divider by 2 (generating 10 MHz).
In total this would mean that when the sync pulse is going from low to high, I
would expect that the total delay from sync high to clock output would be:
1x 0,390625 ns (1/2.56 GHz)
15x 1,5625 ns (1/640) MHz
However, when I measure with the scope, the delay is 27,2712 ns. This is a
difference of 3,44 ns. Do you know where this delay could be coming from?
AI will assume that all of these measurements were made at the pin on the AD9517
package. If so, then some of this may be coming from the fact that you’re using
two cascaded channel dividers and the formula that you’re using was intended
for the channels where there is only one channel divider in the chain. There
may also be a propagation delay difference based on the output logic type.
Anyhow, no need to worry. It’s possible to adjust the phase of the channel
divider in 1.56 ns steps (1/640 MHz). This is done in the “Phase Offset
Divider” settings in the register map.