AD9510: Outputs not in Phase

Document created by analog-archivist Employee on Feb 23, 2016
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for evalution board AD9510, on the CLK1 input 1001.6 MHz, ratio 8 for output5
and output6 equal 125.2 MHz. For on/off, on/off ext. clock (1001.6 MHz) have
shift phase between output5 and output6 equal 90 or 180 or 270 or 0 degree.

 

It is necessary to do a register update AFTER each write to the Soft Sync bit.
That is, it is necessary to load the Soft Sync bit by updating the registers
with the 0x5A<0>=1.

Here is my recommended sequence:

1) write all of the desired parameters for the AD9510
2) write 0x5A<0>=1 (update internal registers)
3) write 0x58<2)=1 (set Soft Sync)
4) write 0x5A<0>=1 (update internal registers)
5) write 0x58<2)=0 (release Soft Sync)
6) write 0x5A<0>=1 (update internal registers)

Try this and see if it fixes the problem.

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