AD9430: Unstable output

Document created by analog-archivist Employee on Feb 23, 2016
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I am using a AD9430 at 176MHz and the output does not look stable using LVCMOS
mode (parallel).
I have heard there may be issues regarding the LVCMOS output at high speeds.
Please can you advise if this is the case?


Any high speed mixed signal board design will require careful attention to
board layout and grounding. LVDS signalling uses differential current outputs
and is in fact used to make easier to transmit high speed digital signals
reliably and minimise cross talk. If you are seeing unstable output (and I
presume you mean the output code is changing), LVDS outputs are not necessarily
the cause of the problem.

Before proceeding let me clarify a nomenclature issue. The AD9430 offers
interleaved 3V CMOS outputs or LVDS output modes (not LVCMOS modes).

For high sampling speeds (>100Msps) we recommend the LVDS outputs and indeed
all the datasheet specs assume LVDS mode.

Are you are seeing noise at the outputs (i.e. multiple bits flickering with the
input set to zero? A common application issue with any high speed converter is
to forget that it has an extremely wide input bandwidth (700MHz in the case the
AD9430) so you will see noise across this entire bandwidth.

Are you using the Eval board for the AD9430? A good starting point is to supply
the eval board with a clean sine wave and perform an FFT on the output, then
you can look at the key specs such as SNR, SFDR, ENOB etc.

You can use the High Speed Converter FIFO board to perform these test with a