AD9280: Minimum clock frequency

Document created by analog-archivist Employee on Feb 23, 2016
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I have a customer investigating the AD9280 - please could you tell me the
lowest rated conversion frequency... and any trade-off operating at lower freq.


We have no minimum specification on the Clock frequency.

Datrasheet specs on SNR, SFDR and distortion in the datasheet assumes a clock
frequency of 32MHz.

We show how THD as a fucntion of clock frequency in figure 8 which remains flat
down to 3MHz. In general for high speed converters, there will be a minimum
clock frequency. The pipeline architecture of the AD9280 uses sampling
capacitors to hold intermediate conversion residues and as the sampling
frequency is reduced, eventually the droop on these sampling capacitors will
degrade performance.

We have no data available on the performance of the part at clock frequencies
below 3MHz. The part will operate at lower clock frequencies with degraded SNR
/ THD however, at some arbitrary low frequency you will start to see missing
codes due to droop in the sampling caps. I would recommend 3MHz as the minimum
recommended operating clock frequency to your customer  - It will go lower but
they are “on their own”.

In terms of power, Figure 10 shows how the total power consumption varies with
clock, drop to 78mW for a 3MHz clock. Further reduction on clock frequency will
bring negligible reduction in power as the analog quiescent current will tend
to dominate.