What are the options for optimum clocking of the AD9249 to ensure proper operation?

Document created by analog-archivist Employee on Feb 23, 2016
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What are the options for optimum clocking of the AD9249 to ensure proper
operation?

 

The AD9249 has a very flexible clock input structure. The clock input can be a
CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being
used, clock source jitter is of the utmost concern. A low jitter clock source
is converted from a single-ended signal to a differential signal using either
an RF transformer or an RF balun. The RF balun configuration is recommended for
clock frequencies between 65 MHz and 520 MHz (prior to CLK divider), and the RF
transformer is recommended for clock frequencies from 10 MHz to 200 MHz.

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