AD9225: Effect of varying the clock period and duty cycle

Document created by analog-archivist Employee on Feb 23, 2016
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Now I revise project of 3 years old (ADC module). And have question. If I will
give to CLOCK input (AD9225) signal with 50 ns CLOCK HIGH pulsewidth and
variable (50ns-1ms, with step of 50 ns) CLOCK LOW pulsewidth. Will this
degradate ADC characteristics in compare with symmetric CLOCK high/low
pulsewidth? Variable means, that for one measure (8Samples to 4MSamples) clock
period set to one value.


The AD9225 relies on a low jitter, clock source with nominal 50% duty cycle in
order to achieve highest spurious and SNR performance. The requirement for low
jitter and duty cycle stability is more critical at highest sampling rates.

The AD9225 was designed and is tested for use with a continuous clock at a
fixed frequency and all datasheet specs are under these conditions. If you
dynamically change the clock frequency and duty cycle you can expect some
degradation in spurious and SNR performance. A certain amount of user testing
will be inevitable in determining exactly how performance will degrade in a
particular application.

I can, however, make a few general comments. The minimum clock frequency for
reliable operation of the AD9225 is 1kHz (1ms period). At highest sampling
rates best performance is achieved with a symmetrical clock. At lower sample
rate >1MHz varying the duty cycle will have less effect on AC performance.
Remember that the AD9225 has a pipeline latency of 3 sample periods.