AD9220: clock input level

Document created by analog-archivist Employee on Feb 23, 2016
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In AD9220 datasheet, the DVDD determines the digital output level. For CLK
input, the high voltage level should be larger than 3.5V. Is it true for 3.3V
DVDD power supply? I use 3.3V level clock and would like to know whether it is


DVDD only specifies the digital output level and the clock always needs to
satisfy the specifications.  Regardless if DVDD is 5V or 3V, the clock input
high level has to be at least 3.5V.  If the customer uses 3.3V levels for the
clock, it may or may not work.   In addition the performance will not be
guaranteed over temperature and supply.  This is a 5V part, therefore the
voltage requirement of the clock is relatively high.  ADI also has 3.3V ADCs
that might fit their needs better.