AD9117: How do I estimate the overall DAC pipeline delay?

Document created by analog-archivist Employee on Feb 23, 2016
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How do I estimate the overall DAC pipeline delay?

 

DAC pipeline latency is affected by the phase of the RETIMER-CLK that is
selected. If latency is critical to the system and must be constant, the
retimer should be forced to a particular phase and not be allowed to
automatically select a phase each time.

Consider the case in which DCLKIO = CLKIN (that is, in phase), and the
RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, Q data is
latched on the rising edge and I data is latched on the falling edge). Then the
latency to the output for the I channel is three clock cycles (D-FF 1, D-FF 3,
and D-FF 4, but not D-FF 2, because it is latched on the half clock cycle or
180°). The latency to the output for the Q channel from the time the falling
edge latches it at the pads in D-FF 0 is 2.5 clock cycles (½ clock cycle to
D-FF 1, 1 clock cycle to D-FF 3, and 1 clock cycle to D-FF 4). This latency for
the AD9114/AD9115/ AD9116/AD9117 is case specific and needs to be calculated
based on the RETIMER-CLK phase that is automatically selected or manually
forced.

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