I have the internal reference clock multiplier(PLL) enabled. Why does spectral performance degrade when using larger values of multiplication on the internal PLL?
The REF CLK multiplier is implemented by a PLL circuit. The output of the PLL becomes the system clock for the DDS.The output phase noise performance of a PLL is impacted by the multiplication ratio. Within the loop bandwidth of the REF CLK multiplier, any noise that is present on the REF CLK source will be gained up in proportion to the multiplication value. This can degrade narrowband SFDR within the loop bandwidth of the PLL, although it does not necessarily degrade the wideband SFDR. The formula for signal degradation within the PLL loop bandwidth is given by db = 20 log x, where x is the multiplication value. The loop bandwidth is typically a few hundred kHz to 1MHz.