Q:

I have the internal reference clock multiplier(PLL) enabled. Why does spectral performance degrade when using larger values of multiplication on the internal PLL?

A:

The REF CLK multiplier is implemented by a PLL circuit. The output of the PLL becomes the system clock for the DDS.The output phase noise performance of a PLL is impacted by the multiplication ratio. Within the loop bandwidth of the REF CLK multiplier, any noise that is present on the REF CLK source will be gained up in proportion to the multiplication value. This can degrade narrowband SFDR within the loop bandwidth of the PLL, although it does not necessarily degrade the wideband SFDR. The formula for signal degradation within the PLL loop bandwidth is given by db = 20 log x, where x is the multiplication value. The loop bandwidth is typically a few hundred kHz to 1MHz.

It is worth noting that the level of degradation you will see is part dependent. When ADI first started adding reference clock multipliers (see the AD9851), they were much more of a convenience feature. In more recent devices (including the AD9958/9 and AD991x series), we have put more emphasis on the perofmrnace of that functional block. It still won't be as strong as if you were to come in with a driven clock already running at the desired sample rate.