AD8129 AD8130: output impedance in power-down mode

Document created by analog-archivist Employee on Feb 23, 2016
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A customer asked why we specify the output impedance of AD8129/30 in power-down
mode as 10pF in the datasheet? Does that mean in power-down mode, the output
impedance is very high for DC and will get lower as the frequency increasing?
Would you please help to clarify this specification?

 

The PD pin on the AD8130 is only intended to save power in "Power Down" mode,
and is not intended to put the output in a high-Z tri-state condition. There is
no buffer on the output to implement the high-Z state. With the PD function
asserted, what happens when another device connected to the output becomes
active depends upon a number of factors, including the magnitude and frequency
of the signal on the output of the active part. If the customer wishes to
multiplex the outputs of several AD8129/30s, the safest bet is to use a
separate device, such as an analog mux, to implement the switching function.

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