AD7960 Test Pattern

Document created by analog-archivist Employee on Feb 23, 2016
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Page 17 of data sheet rev c
 
set the enables to 0100X, to get test pattern out of the adc serial  link.
 
Great, can include that in the self test code fo the unit to prove the adc 
interface is working and meeting timing,
BUT
 
what is the pattern ?
 
I can’t make a checker of the pattern unless I know the pattern ,
 
I guess PRBS or walking ones or alternate 1, 0 , 1
 
but, can’t find it specified anywhere,
 

 

The AD7960 generates an 18-bit pseudo random test pattern based on the
polynomial series - . To generate this pattern, you need to power-up the AD7960
and set EN[3:0] = 0100. Then Initiate a conversion CNV± and run the CLK± at
200MHz (max up to 300MHz). The pseudo random generator is reset into a known
state at the start of the first conversion. At the end of conversion, the
pseudo random number is loaded into the LVDS block instead of the 18-bit
conversion result. The pseudo random number can be read back the same way the
conversion result is read back. To exit this mode, you need to change EN[3:0]
from 0100 to any other combination mentioned in the datasheet.

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