AD7899 - CS and RD tied permanently low

Document created by analog-archivist Employee on Feb 23, 2016
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Can the CS and RD inputs be tied permanently low in single device designs.

 

The AD7899 needs to see an edge on the RD signal to clock out the data. This
can be achieved by either using one signal to drive CS and RD, or hold CS low
and pulse RD. You will also notice the example of where the EOC signal can be
used as the RD input as per page 11 of the datasheet EOC Mode.

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