Power-On-Reset problem on the AD7812

Document created by analog-archivist Employee on Feb 23, 2016
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After power-up it may happen - the exact circumstances are not quite clear -
that the AD7812 enters some indefinite state. Starting an conversion and
reading out the result of the previous conversion produces false values.It
seems the data shift register was initialy loaded with a certain value, and
this value is shifted out every time a new conversion is started - no matter
what channel is chosen. This can only be explained with a complete disturbance
of the conversion- and write-to-shift-register- function. We  tried to get the
AD7812 out of this state by writing all possible patterns to the AD-control
register. We found out that we can enter a correct state  of operation if we
set PD0 and PD1 to '0' (once during a so called power-up-routine) before
starting normal write-read-operation.
We can definitly say there is no input (digital/analog) which is above VCC 
even during power-up. VCC is rising from 0 to +5V within about 40 ms.
Do you know this problem? Is our 'selfmade' power-up procedure a legal means to
correct our problem ?

 

There is a known issue with the power on reset on the AD7812. Below is more
complete description of the problem:
If Vdd drops down to the region 0.8-1.2V and is then brought back up again, the
part is not able to reset itself properly and the device will lock up and only
output the last converted code. The solution is to ensure that Vdd drops all
the way to 0V when the power supply is cycled. There are number of ways in
which this can be achieved. The simplest is to add a resistor across the power
supplies but this obviously increases the power supply of the circuit as a
whole. A FET current source across the power supplies can also be used to
discharge the large capacitors which are used for power supply decoupling.

The AD7812 is currently (7/6/2000) being re-designed to resolve this problem.
There is no confirmed schedule for release of the re-designed part.

At the moment I can confirm that cycling the Power Down bits P1 and P0 will
resolve this problem.

-------------------------[07/07/2000] - Donal Geraghty
Yes the customer has found our Power-On-Reset problem. The good news is that on
the 7811/12 , you can get around it in software in exactly the manner he
describes. Exercising the power down bits to effectively power-down the part
AFTER Vdd ramp-up resets the internal oscillator which controls conversion.
Once reset the oscillator is fine and the part will work as normal.
FYI  On the other members of this family , the 7810/23 and 7813/19, you can’t
power-down the parts in software. Power-down happens after a conversion is
complete depending on the status of CONVST. But with the Power-On-Reset problem
a conversion may never happen because the oscillator ‘locks-up’.  Hence the
only way out is to power down and up the part.

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