AD7825: RD permanently low

Document created by analog-archivist Employee on Feb 23, 2016
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The RD signal is it intended to transfer
the data on the bus
or can be tied always to low level?

 

If you are using the AD7829 or the AD7825, the RD/ signal is essential for the
operation of the device as the falling edge of RD/ is used to latch in the next
channel address.  The CS/ and the RD/ signals are internally 'ANDed'
together  and the case that CS/ and RD/ are low puts the conversion data onto
the bus.  Therefore, CS/ can be tied permanently low and just the RD/ signal
toggled to access the data.  The rising edge of RD/ puts the bus back into
tri-state. 

It should be possible to operate the AD7822 without using CS/RD and EOC as
explained below:

Where CS and RD must be tied permanently low.  In this case, the data bus is
always active i.e. it never goes into 3-state.  The EOC signal is an output
from the AD7822 and can be used if you like but this is mainly to inform the
user when conversion data is available in the output register.  The falling
edge of EOC puts the conversion data into the output register.  This occurs
420ns after the conversion has been initiated.  The EOC is ideal  for latching
the data into the DSP or controller as no external signals are required - but
again this is not essential.

By keeping RD and CS permanently low, the AD7822 will have complete control of
the bus all the time i.e. no other part will be able to take the bus.  After
the falling edge of EOC, the conversion data will stay on the bus until the
next falling edge of EOC, i.e. until the next conversion data is output onto
the bus.
This is because, a rising edge of RD puts the bus into 3-state, thus freeing
up the bus for use elsewhere.

t3, the min time between the rising edge of RD and the next falling edge of
CONVST, is effectively the time from putting the bus into 3-state on the RD
rising edge until the next conversion is initiated, or the 'quiet time' between
conversions. It is not important for a reset, but should be allowed between
latching data and initiating the next conversion.

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