AD7799: Problems with communications via serial interface

Document created by analog-archivist Employee on Feb 23, 2016
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I use AD7799 in recommended circuit in continuous conversion mode on 1 channel
(1st). Sometimes (perhaps due to EMI) I have some problems with serial
interface. recommended way of reset (32 '1') works, but I can't determine the
moment, when I must reset device. For example, my device shows 1.0 V (in
unipolar mode) and I have some understandable deviation, then suddenly it shows
(permanently) 2V or more (with deviation too). Real input voltage is 1.0V, but
ADC shows erroneous results. While testing, I recognize, th? error, because I'm
sure, that there is exactly 1V. Have I any other ways to recognize, that ADC
works erroneously ? All functions are available, serial number (0xX9) is good,
but results are bad... What can you recommend here ?


The SPI interface is particularly sensitive to noise, here are some
recommendations for investigating communications issues:

The most likely reason for reading incorrect data from the AD7799 registers is
a spurious (extra) clock pulse appearing on the SCLK line. The SPI interface
can be particularly sensitive to interfering noise. This can be avoided by
careful layout and bypassing, clean power supplies etc (take careful note of
recommendation on page 26 of the datasheet) .

The time between t1 and t2 can be 0 nSecs min (see timing specs page 8 of
datasheet). t1 is the time between CS going low and DOUT/RDY becoming active.
Once this time has elapsed, you can begin applying the SCLK pulses. 

When SCLK goes low, the AD7799 will place the first bit of the 24-bit word on
the DOUT pin. You can either latch in the bit when SCLK is low or on the SCLK
rising edge. One bit of data is placed on the DOUT pin for each SCLK pulse. 

We suggest that you should probe the serial interface lines to ensure that the
correct number of SCLK pulses are applied to the AD7799. 

If SCLK can be idled high when it is not being used, this usually simplifies
the interface. After CS is taken low, the first SCLK transition will be a high
to low transition. At this point you should see the first bit on the DOUT pin.
The data can now be read into the FPGA or on the SCLK rising edge. 

Also, DIN should be idled high when it is not being used. So, after power up,
we suggest that you reset the AD7799 by writing 32 1s to the device. 

Then attempt to read some of the on-chip registers to confirm that the read
and write routines are working correctly. 

If you still cannot read the correct information from the registers, then you
will need to verify your code by connecting a scope to SCLK, DIN of the ADC to
verify that the correct information is being sent to the ADC as per fig 3 and
fig4 on page 7 of the AD7799 datasheet.

You could try putting a small value cap from the SCLK pin to AGND. If a
capacitor on the SCLK fixes the problem, then it is likely that you have excess
noise on your board. The transistors that make up the serial interface are
actually quite fast and can react to high frequency noise/interference.


- If the SCLK is very noisy and has multiple transitions on each clock edge,
then the same data bit will be input or output several times which will cause
the ADC and the controller to lose synchronisation.


- If the clock edges are very fast, and the SCLK line is quite long then you
can get overshoot/ringing, reflections, etc causing false transitions on the
line. A little Series resistor may help here.