AD7793: Continous conversion mode

Document created by analog-archivist Employee on Feb 23, 2016
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On page 22 of the AD7793 data sheet rev A. one can read, that while continuous
conversion mode ?the user must ensure that the data register is not being
accessed at the completion of the next conversion, o else the new conversion
word is lost.? But in that case, is then the current data invalid or corrupted?
How can I avoid accessing the data register at the ?completion of the next
conversion?? Having pin OUT/RDY already low and then Reading the status
register RDY-Bit can cause the same effect?

 

In continuous conversion mode, DRDY will go low when a conversion is complete
(and the RDY bit in the status register is set). The customer then has a period
of time equal to 1/update rate - 0.8 ms to read the data register. This will
ensure that all conversions are read. If the customer begins a read but has not
completed the read within the allocated time, the data register retains its
contents i.e. the register is not updated with the next conversion. Instead, it
holds the present contents until the read operation is completed. Then, it
updates again when the next conversion is available. This ensures that the
customer only ever reads valid conversions.

So, when the RDY pin goes low (or RDY bit indicates that a new conversion is
available), the customer should begin the read immediately. If the customer
does not read the data register, DRDY will stay low. It will go high for a
period of 0.8 ms if another conversion becomes available at the customer has
not begun the read. During this period, the data register should not be read -
the user should wait until DRDY goes low again. If the data register is read
during the 0.8 ms interval, then a valid conversion will be read.

So, in summary, monitoring the RDY pin/bit prevents the customer from reading
invalid conversions.

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