AD7793 output rate to input clock ratio

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
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We clock the AD7793 with an external 128kHz clock which is derived from the
microcontrollers clock. Therefore we expect no runaway effects between uc timer
and AD7793 output data rate (10Hz by the way). But we see a difference in the
DRDY signaling (over a time scale of several minutes and hours) and therefore
suspect that the output data rate of the AD7793 is not exactly 10Hz but
something nearby. The AD7710 which we use in another project has for example
10.00064 Hz instead of 10 Hz. Could you please supply us with the exact divider
between input clock and the output data rate at 10Hz?

 

The output data rate is slightly less than 10 Hz. It is 9.99 Hz. Attached is
the filter Excel model for the AD779x family. I have set up the model for the
10 Hz theoretical output data rate. As you can see from the model, the actual
output data rate is 9.99 Hz and the settling time is 201 ms.

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