QI am trying to run AD7760 at 5Msps output rate, and are confused by the timing
parameters in the datasheet.
I run the converter at MCLK=ICLK=20MHz, How do I configure the timing?
AWith regard to this mode. We have to look at the timing involved in taking data
out at this rate.
The mode that you are enquiring about is one which takes the data from the ADC
at 5MHz. This means the data is not fully filtered by the digital filter path
and bypasses the final stage in the filter which is the longest filter.
This mode is not covered by our specifications listing which is run at 2.5MHz
for fully filtered data.
The interface timing is similiarly tested relative to operation at 2.5MHZ
output data rate, this is why there are contradictions.
The fastest rate of use of the AD7760 is with the modulator output. This runs
at 20MHz rate and only the first 16 bits of the data output are required (due
to quantization noise).
We did not specify the number of bits for the 5MHz rate, so it would also be
confined to 16 only or not. If so then the second part of the read cycle after
each DRDY falling edge would not be necessary and so the timing requirements
would be loosened.