### Q

We have a customer who would like to know how does the Gain CalibrationRegister influences the conversion results in AD7730. He want to get the

calculation formula.

### A

In unipolar mode, the relationship isData = [(0.75 × VIN × Gain/VREF) × (2**23) – (Offset_Reg – 0x800000)] ×

Full_Scale_Reg/0x400000 × 2

In bipolar mode, the relationship is

Data = [(0.75 × VIN × PGA_Gain/VREF) × (2**23) – (Offset_Reg – 0x800000)] ×

Full_Scale_Reg/0x400000 + 0x800000

Where

Data = digital conversion

VIN = applied analog input voltage

Gain = PGA gain setting

VREF = reference voltage

Offset_Reg = value contained in the offset register

Full_Scale_Reg = value contained in the full-scale register

The nominal values of Offset_Reg is 0x800000 and of

Full_Scale_Reg is 0x555555.

The 0.75 number will vary slightly from part to part because of

manufacturing tolerances.

1 LSB of the offset register is equivalent to approximately 1.3 LSB of the data

register, assuming the nominal full-scale coefficients are present. The exact

value varies slightly from part to part, and the ratio changes if the

full-scale register coefficients are modified.

The exact ratio can be derived by dividing the value in the full-scale register

by 0x400000. This gives a value close to 1.33 with the nominal full-scale

coefficient of 0x555555. But if the full-scale register is modified by the

user, the ratio changes. This occurs since the offset removal is performed

before the gain scaling when the ADC is adjusting the converter output.

The full-scale register can be interpreted as a multiplication factor, whose

value equals (full-scale coefficient/0x400000.) Since the scaling is done after

the offset register is removed, the relative weight of an offset register LSB

is different to a data register LSB.

The nominal value of 1.3 for the gain scaling is because the input signal is

attenuated by 3/4 as part of the ADC conversion. A 4/3 scaling is then required

to digitally compensate for this. (This is normally transparent to the user;

it’s only when manipulating calibration values that this can become apparent.)

The signal flow can be viewed as

[Input Signal] -> [PGA] -> [Attenuation by 0.75] -> [ADC Conversion] ->

[Subtract Offset] -> [Scale by FS/0x400000] -> [Data Register]

If the system offset calibration is done using the ADC’s system zero-scale

calibration mode with the systems zero-scale point applied as input voltage,

then this scaling factor does not need to be accounted for, since the ADC

calibration routine will write the correct value into the offset register. It’s

only if calibrations are done using regular conversions (that is, a result is

written into the data register) that a scaling factor is required before

writing into the offset register.

For the full-scale coefficient or full-scale calibrations, it is a simple

scaling coefficient, so to increase the gain of the ADC by 10%, the full-scale

coefficient needs to be increased by 10%.