FAQ: What is the cause of a "Core fault detected before halt at address" error message?

Document created by ColinJ on Feb 25, 2010Last modified by ErinH on Sep 14, 2016
Version 7Show Document
  • View in full screen mode


What is the cause of a "Core fault detected before halt at address" error message?




The "Core fault detected before halt" message is the debugger reporting the core fault bit is set in one of the emulation control/status registers. This is not necessarily a catastrophic event, it could be the processor simply executed invalid instructions when coming out of reset before being halted.


In other cases, this is a catastrophic event. e.g. If, while debugging, the code causes a double core fault the emulator will display a similar message. However, in this case, there is no recovery possible. The most likely cause is that an exception has occurred while already executing the exception handler (or attempting to).


If the Core Fault is occurring immediately when you connect to VisualDSP++, it may be that the target board is booting bad code. You can determine if this is the case by changing the Boot Mode of the target to a different setting and checking if the behaviour persists.


A good technique for narrowing down the cause of a core fault is to use the Settings->Preferences menu and uncheck "Run to main after load". This will simply load the DXE without running it. If the load occurs correctly, start single stepping through the code until a failure occurs.


You could also try to use the Settings->Target options menu and check the "Verify all writes to memory" check box (in addition to the above). This will verify that the code downloaded to the target actually makes it to the target memory.


Another option is to use the statistical profiler. Before downloading, open the statistical profiler window. Then start the download (with the "run to main" option checked). In some cases, if there is a core fault, the statistical profiler will indicate the address or a function near the address where the core fault occurs, this can be seen because the reported address will be almost 100% of the profile.


One other thing to try, if you are using an HPPCI-ICE or an HPUSB-ICE, is to adjust the JTAG Frequency via 'Settings'->'JTAG Frequency'. Communication with the target may be more stable at a different frequency.


If you are still having problems narrowing down the issue please contact our private support channel at: processor.tools.support@analog.com providing the following information. Details of your version of VisualDSP++ along with a screenshot of VisualDSP++ with the disassembly window open when the Core Fault error is generated.