AD7716: Relationship between SCLK, FCLKIN and resolution

Document created by analog-archivist Employee on Feb 23, 2016
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I am facing a 89c52 to master the ADC7716 .
1.The sclock is abut 3MHz (the max I can give him)
2. cut – off  :  73Hz
3. input : regular E.C.G signal

? in slave mode : is a FCLKIN needed ???

 

CLKIN is required in both master and slave mode.

CLKIN is used to drive the modulator and internal digital filters. All
datasheet specs are with an 8MHz master clock. This can be most easilty
achieved by connecting an 8MHz crystal between CLKIN and CLKOUT and appropriate
capacitors to ground as specified by the crystal manufacturer. The sample
update rate (how often /DRDY goes low) is a direct function of CLKIN.

Output data rate = 3.81 x Fcutoff =  Fclkin / (7168 x N)  where N is the
decimal equivalent of FC2, FC1, FC0.

SCLK is used to clock data into and out of the part. SCLK may be generated by
the AD7716 (master mode) or by an external processor (slave mode). SLCK has no
direct influence on the output sample update rate, however the user must ensure
that SCLK is fast enough to clock out data from all channels before 

Master and slave mode simply determine which device (AD77016 or micro)
generates the SCLK and RFS signals.

Assuming Fclkin =  8MHz, N = 3 sets up a cutoff frequency of 73Hz and an output
update rate of 279Hz. From Table I, the noise is 7uV rms. Peak to peak noise is
6.6 x 7uV = 46.2uV pkpk

With an input range span of 5V (+/-2.5), the peak to peak resolution is:
5V / 46.2uV = 108 225 codes.

To convert this number of codes into number of bits:
Log10(108225) / log10(2) = 16.7bits.

So in this mode, the AD7716 offers 16.7bits peak to peak resolution. Some
engineers like to use rms noise instead of peak to peak noise, and this is
called “rms resolution” or “Effective resolution”. For more background on the
difference refer to AN-615.


Finally let’s see if your SCLK frequency is fast enough. You have an output
update rate of 279Hz, which means you must read out all data bits within 1/279
= 3.6ms. This will require 129 SCLK cycles

With a 3MHz SLCK, the total time to read out all four channels is 129 / 3MHz =
43us. This is well within requirements.

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