AD7715: Debugging the output

Document created by analog-archivist Employee on Feb 23, 2016
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We have an AD converter, it's the AD7715.
We don't manage to have the right output.
If we put on the input pin 0.0 Volts, the converter indicate that we are on the
level 65535.
We don't understand.


65535 corresponds to the full-scale (all ones) output of the ADC. I suspect
that something fairly simple has gone wrong in your circuit. First check
connections at all pins, look for power, reference, ground and analog input.

After power on, the default state of the AD7715 is output a conversion every
0.0166seconds (60Hz update rate). With nothing else connected to the interface,
place a scope on the /DRDY pin and you should see it toggling at a frequency of

After confirming operation of the AD7715, next test out the interface. Try to
read the default values from the status register. After power up the status
register should return 28Hex. If you don't get this value, you need to look in
details at the hardware interface.

When using the digital interface of the AD7715, it is critical that you provide
the correct number of clock cycles when reading from or writing to the control
registers. If you provide one extra clock cycle and then write to the part, you
will put the part into an unexpected state. Similarly if you are reading from a
24bit register and you only provide 20 clock cycles, the interface will be out
of synchronisation.

One possible cause is spurious clocks on the SCLK line. The interface expects
the first bit of any write to be a zero. If the first bit is a one, it will
ignore all writes until it sees a zero. If after performing a read, you leave
DIN low, any spurious clocks on the SCLK line will clock a bit into the
Communications register. The next time you write eight bits to the
Communications register, only the first seven bits will be loaded and the
eighth bit will be interpreted as the first bit of a subsequent write. You can
avoid this problem by pulling DIN high after each write.