AD7710: Serial interface

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

Sometimes the ADC AD7710SQ seems to start in an "unusual mode" after power up.

The serial output bits are delayed by one serial clock cycle or the serial
configuration input data are read or shifted one bit left (in advance).
I use the external clocking mode.

As powercycling is not an option how can I reset the chip by software ??


The following procedure is recommended to check if the serial interface is okay.
Using the Control register as a shift register:
1 Carry out a read from the Control register. You should read back the default
value of 000146hex
2 Write to control register (if SYNC is low then the part won't act on the
write operation)
3 Read back value from the control register (MD2~0 may have changed but the
other bits should be the same)

In addition, to prevent noise etc corrupting the serial interface, we recommend
pull ups on the TFS and RFS lines and a pull down on the SCLK line (since a
falling edge clocks in data.)

In addition, you can use self calibration to reset the interface after power