AD7714: Saturating the I/P channel

Document created by analog-archivist Employee on Feb 23, 2016
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When the AD7714 is sampling data if the input on the AIN1 line exceeds 3.5V
with reference to AIN6 the input line and also the output of the AD8555 will
stay fixed at this voltage ( in both buffered and unbuffered mode), even if the
input to the AD8555 is dropped enough so that under normal operation its output
would be less than 3.5V. If the AD7714 has not started sampling data the output
of the AD8555 if free to go above and below 3.5V. Is there are reason for the
AD7714 saturating at 3.5V and its input not being able to go lower once this
voltage level has been reached? The device is operating in Unipolar mode.

 

You may need to set and clear the FSYNC bit (in order to clear the digital
filter ),  when you saturate the channel - try the following when the analog
i/p has returned to it’s VREF/GAIN i/p range.

1)Write to the comms register, selecting the mode register.

2)Write to the mode register setting FSYNC high and channel gain(when this bit
is high, the nodes of the digital filter, the filter control logic and the
calibration control logic are held in a reset state)..

3)write to the comms register, selecting the channel and a write to the mode
register.

4)write to the mode register setting FSYNC low and channel gain( when the
FSYNC  bit goes low, the modulator and filter start to process data and a valid
word is available in 3 x 1(output update rate) i.e.,the settling time of the
filter)

5)Poll the DRDY output.

6)Write to the comms register to select a read operation of the data register.

7)Read the data from the data register.

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