QI got some samples of the AD7691 and connected it to the SPORT of an
ADSP21161N. I found a strange behaviour of the ADC and I have no idea why. I
connected a constant voltage to the positive input of the device (the negative
input is grounded).
The SDI pin is held high at 3.3V. The problem is that the lower 4...5 bits of
the output data are always stuck at 0. The higher bits are sometimes changing.
Thus, the effective resolution is not 18 Bits but only 13 or so.
But: If I lower the input voltage to let' say below 10% of VREF or so
(REF=VDD=5V), then the lower bits get alive.
AAD7691 is a Successive approximation ADC. You may know that a SAR converter
converts by a series of bit trials, deciding
the value of the MSB D, then D, D, D ... down to D.
Internally, each bit of a DAC is set, and the result compared to the Analog
input. The result of this comparison determines the bit value. One of the
prerequisites for a SAR converter is that the Analog input (and the reference
input) remain "constant" for the each bit trial. If you look at figure 25 of
the datasheet , you wil see that the the VREF is connected to the internal
device constatnly while the Signal inputs are disconnected dure converstion
If one of the bits is incorrectly set (e.g. bit 6 is set to a 1 when it should
have been a 0, due to a noise spike during that bit trial) then all of the
following bits will be set to either all "0" or all "1", to try to reduce the
DAC output to the correct value.
The sample and hold at the Analog input ensures that the Analog input to the
ADC remains constant during the conversion. However, there is no sample and
hold at the reference input. Indeed the Vref pin is a dynamic load for the
amplifier or reference that is driving the pin - as stated in the datasheet
For this reason a Capacitor of 10uF or greater , right at the inputs of the
VREF is required to keep the VREF inputs noise free during conversion.