AD7689 digital interface timing

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

I double checked with spec that there is no timing graph except some simple
text to descrip the modes of  "Reading/Writing During Conversion, Fast Hosts "
and "Reading/Writing During Acquisition, Any Speed Hosts "

Would you tell the details of timing about these 2 modes?

 

This family of ADCs have the data access gated by the end of conversion (EOC),
tCONV(max). Data reads and writes (CFG) need to occur from EOC to EOC.
Basically if data access is only taking place during conversion, the host is
limited to tDATA time which is limited since when conversion starts (CNV
rising) internal circuits take over and force data access in this time. They
can read right up to tCONV(max) but can have 1 of 2 things happen.
1. Corrupt data as smaller weighted LSBs are sensitive to digital activity.
2. Miss LSBs as the tCONV(max) is covering hot temperatures and slow process
material. The actual tCONV(max) can be 100 ns (or more) < spec so new MSB will
overwrite whatever bit is on SDO

Data access during acquisition is for customers using both slow or fast hosts
since the host is controlling CNV and they have as much time as needed for data
access.

One thing to make certain is to check to make certain they have released
material. Discard any X-grade material as these have a different digital
interface!

For this family, it is always a pipeline of:
configure (n+1), acquisition/conversion (n), readback (n-1). This means that
for current (n) acquisition /conversion phase, the CFG is for the next (n+1)
acquisition and conversion phase and data readback is for the (n-1) conversion
that just occurred. CFG and data readback (SDO) occur at the same time with CFG
updating on 1st 14 SCK rising and SDO shifts on SCK falling.

Attachments

    Outcomes