AD7685: Not seeing expected resolution

Document created by analog-archivist Employee on Feb 23, 2016
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Problem with the AD7685. The conversion is only on 12 bits. I work in mode 3
wire with no busy indicator. The last 4 LSB bits are always high. I read in
hexa 0xXXXF. What are the conditions which may cause this problem.

 

The ADC needs separate REF decoupling cap placed as close as possible to the
REF pin. Keep in mind, this is not a supply decoupling cap; this is part of the
REF circuit that we cannot include on the ADC due to the size and value
required. Take a look at fig 27 - this cap must be placed as close as possible
to the ADC. Inadequate reference decoupling / decoupling too far away from the
Ref pin is generally the main reason why our customer's have difficulty getting
specified resolution.

Here are some additional tips for best performance.:


1. The Ad7685 Ref & Vdd should be reference to the same ground ( ANALOG GND).
VIO can be referenced to a digital ground if you wish.
2. You can use one ground plane or two if you want to separate the Digital and
analog signals.( which you do )
3. The ANALOG GND plane should be underneath the AD7685.
4. Fast switching signals ( CONV and CLK) should not be near the ANALOG signal
paths and if possible the digital plane should be used to shield the fast
switching signals. This will help to reduce the noise/spikes due to switching
on the CONV.(like we talked about this morning w.r.t the scope plot)
5. Power supplies should have larger tracks to reduce impedance and also reduce
the influence of glitch’s on the ADC.
6. Take note of all coupling considerations for the power supply line and the
REF inputs from the datasheet. Use 10uF and 100nF Capacitors for decoupling
noisy systems on all lines.
.

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