AD7657-1 DCINA input set-up and hold times & t17 minimum and what is t20?

Document created by analog-archivist Employee on Feb 23, 2016
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I use the AD7657-1 in serial mode.

(i) Could you  please supply information on the DCINA input set-up and hold

(ii) and a minimum time for t17 (Dout from  SCLK rising edge)?"
This information is available for the AD2S8557
(iii) There seems to be confusion about what parameter t20 is. Can you confirm


(i) On confirmation from Product-Line Engineer, the simulated set up times for
the DCIN pins with
respect to the SCLK rising edge is 12ns and the hold time with respect to the
SCLK rising edge is 6ns.
These are simulated results and should be used as indications/typical.

(ii) The AD2S8557 also provides a maximum of 15nS (i.e. td3, which corresponds
to AD7657-1's t17).

(iii) t20 is the hold time for the data out from the AD7657 on the DOUT line.
It corresponds to th2 on the TI part.