AD7655: CONVST asstered before conversion

Document created by analog-archivist Employee on Feb 23, 2016
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I have a question to the timing of AD7655 in master-mode.
Does the following operational sequence function?

MASTER MODE:
In the first run an low-impulse on the CNVST line must take place to start the
automatic conversions.
'Start':
- wait until BUSY (or EOC) goes high
- store the value of the channel A
- change A/B
- wait until EOC goes high
- store the value of the channel B
- change A/B
Goto 'Start'

Only does one impulse on the CNVST line have to take place, to start all other
conversions?

 

In NORMAL mode you need to apply a low going pulse on CONVST\ for EACH
conversion in e frequency of CONVST is equal to the conversion frequency. The
internal clock inside the AD7655 is only used to take the conversion from start
to finish but the user has to start each conversion with a low going pulse. The
CONVST\ signal does not need to be a short pulse. It can have a duty cycle of
50%. It is only the falling edge that is important.

In IMPULSE mode you only need to apply the first low going edge on CONVST\. If
you hold CONVST\ low after that, a new conversion will start each time the BUSY
line goes low. This will result in an overall conversion rate of around
888kSPS, but this is subject to quite a wide tolerance since the frequency of
the internal clock is not very precise.

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