QI am working on a project and am using an AD7484 14bit SAR ADC.
The device is running in connection with a FPGA, and later with a CPLD.
In order to minimize the FPGA/CPLD design, I did not configure the 7484, i.e.
I did not write any offset value to the offset register, because I did not want
to use bidirectional buses in the project.
However, digitizing the input results in errors. When the input goes below a
certain limit, the digitizing result is not changing
continuously (it remains on a constant value although the input voltage changes
continuously) down to a certain voltage, and starts a more or less linear
operation again on further decreasing input voltage.
My questions are now:
- Is it always necessary to initialize the 7484, or has the register a reset
value? This is not mentioned in the data sheet.
- Is it possible that such a behaviour described above results from not
initializing the device, or may this have other causes?
P.S.: it must be mentioned that we incidentally had linear operation with the
device twice after switching the system off and on again, but this is not
AThe AD7484 requires a reset after power on - no other initialization is
The AD7484 does not have an internal POR circuit and relies on a rising edge on
/RESET after power has been established. As background, the AD7484 uses error
correcting logic in order to achieve 14 bit no missing code performance and it
is critical that this logic is reset to a known state after power on to ensure
We recommend an ADM809 to drive the /RESET pin. Of course you could drive the
/RESET pin from your CPLD.
Lack of a RESET signal is the most likely cause for such a large number of
consecutive missing codes. If there is a valid RESET signal applied, the next
few things to check are the analog input driver (AD8021 is recommended),
Reference (AD780), then power supply decoupling and signal grounding. If we get
to that stage it would be useful to review a schematic and layout.