AD7305: Settling time

Document created by analog-archivist Employee on Feb 23, 2016
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What happens if there are two write cycles with the second cycle done before
the first conversion is achieved ? Is the first cycle interrupted ?
For instance, how is the output if we write 0xFF then 0x00 and then 0xFF in
less than 1 µs ?


There are two distinct aspects to consider here; the interface timing and the
settling time of the DAC.

Referring to the interface timing on the AD7305 on fig 4 of the datasheet. The
minimum time required to complete a write to the DAC register is determined by
the setup and hold time of the data, address and load lines: Tsetup + Thold  is
60ns for 5V operation and 90ns for 3V operation. If the setup and hold times
are violated, the data in the input register and/or the DAC register will be

On the rising edge of /LD data is latched into the DAC register and the DAC
output will start  to slew to it’s new value with a typical slew rate of
3.6V/us. The DAC output is guaranteed to settle within 2us for a full-scale
transition with a 4V reference and 0.1% accuracy (refer to fig 12 for typical
performance). It’s useful to note that the DAC register directly drives the
switches of the internal resistor ladder, the settling time is mainly due to
the output amplifier.

It is not necessary to wait until the DAC output has fully settled before
writing the next value to the DAC register; if the DAC output has not fully
settled before the next /LDAC rising edge, the DAC output will simply slew from
whatever value it is currently at.

In theory you can update the DAC register at a rate of about 10MHz, but large
output transitions will be slew rate and settling limited. Higher DAC update
rates will produce more transition noise and digital feed-through at the output
and degrade AC performance accordingly.