AD7298, SPI at 20Mhz clk interface and t4 timing issues

Document created by analog-archivist Employee on Feb 23, 2016
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For SPI interface up to 20MHz speed. Timing  t4 (Data access time after SCLK
falling edge)
can be up to 35ns, appears to fall short with an half clock period of 25ns.
This renders impossible the usage of the rising edge to sample the incoming
data in the SPI master, and if using the next falling edge,
than we have no way of getting the last bit read. Can you please comment and
suggestions

 

This is the worst case scenario characterised as stated below.

(1) Temperature range -40 to 125 degrees C.
(2) Your Vdrive of 1.65v to 3V
(3) the load capacitance of 15pF at output (see note 1), p5 data sheet rev.B

(4) SPI dictates the protocol, speed can vary. However for this device, 20MHz
is the max. In practise, to give some safety margin due to PCB layout/routing
and delay etc. In practise one would factor this in and to have an option to
scale back a small bit for precautionary measure.

With the above being factored in, it look o.k.

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