AD7176-2 Settle in a Single Cycle

Document created by analog-archivist Employee on Feb 23, 2016
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Can the ADC be configured to settle in a single cycle?

 

Yes, setting the SING_CYC bit will allow this. It should be noted that the
Sinc5+Sinc1 filter will settle in a single cycle at output data rates of 10
kSPS and lower regardless of whether the SING_CYC bit is set or not.

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