QI have setup the ADC to convert sequentially the diff channels AN1+2 and AN3+4.
I have also configured it to append STATUS reg to the 24 bits ADC data to
determine which channel that has been converted.
CONFIG_REG = 0x800300
MODE_REG = 0x1801E0.
Problem: When I try to detect which channel that has been converted the STATUS
bit0 is always stucked to 1 in my SPI register, even if I can see on the
oscilloscope that it is shifting between 0 and 1.
It seems like the MSDA is shifted to fast from 0 to 1 after the last rising
edge of SCLK so my microcontroller (SAM3S) cannot detect it.
Any suggestions on how to deal With this problem?
AThe issue is that the processor is too slow to detect the LSB.
When the ADC has output the conversion and the contents of the status register,
the DOUT/RDY pin stops functioning as a DOUT pin and begins functioning as a
DRDY pin. This happens some period of time after the last SCLK rising edge.
This same SCLK edge to used to latch the LSB of the status register. If the
processor is slow, it is possible that the DOUT/RDY pin has started functioning
as a DRDY pin so the processor latches the value of DRDY which is '1' rather
than latching the LSB of the status register. With this slow processor, the LSB
of any read (from an on-chip register or a conversion) will be zero.
So, you need to use a faster processor. Another option is to bit bang i.e. use
general purpose input/output pins to replicate the serial interface. Using this
method, you can read the bits a period of time after the SCLK falling edge
rather than using the SCLK rising edge. So, the correct bits are always read.