QI have 4 AD7175-2 connected together to convert 4 analog signals. The output
datarate is different slightly for each ADC. So I have to synchronize these 4
ADCs for simulatanous sampling. I use continous read mode. When I do a sync
periodically the continous read mode is canceled . I have to sample data with
1. How can I keep synchronisation of these four ADCs? How can I set the ODR to
2.I tried to use single conversion mode, but the maximum datarate was below
10kSa. Is it possible to increase the output data rate in single conversion
mode up to 20kSa?
A1. The output data rate can be decreased to 20kSPS by the following procedure:
i. Set the ADC output data rate to 25 kSPS.
ii. Set the ADC to continuous conversion mode. No need to use continuous read
iii. Use an external SYNC pulse running at 20 kSPS to control the sampling rate.
iv. Each ADC can use its internal clock as the ADCs are synchronised for every
In case you wouldn't like to provide the SYNC pulse but instead are going to
provide a shared clock you can adjust this clock speed down to make the output
data rate 20 kSPS, as you mentioned in your previous mail. While the lower
limit on an external clock is not specified in AD7175-2's datasheet, it is no
problem running the ADC significantly slower than 16 MHz. Our product engineers
did some testing at 2MHz for example.
2. Regarding the single conversion mode, you can run the part up to 50 kSPS in
single conversion mode although in reality there are delays with writing to the
part and startup etc. That means it is closer to 40 kSPS max. However, I would
not using single conversion mode for this application.