ad6654: I/Q data output pairs

Document created by analog-archivist Employee on Feb 23, 2016
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I have a problem with your AD6654 Evaluation Board and I hope you can help. I
want to understand the outgoing I/Q data of the AD6654 Chip. For this purpose I
have chosen Parallel Port C and “16Bit Interleaved I,Q” on the Port Setting
Page of your Software.
To watch the data on parallel port C, I used a logic analyser on the data Pins
PC0 to PC15, PCIQ and PCGAIN.
The Problem is, I want to use the “Interleaved I/Q Mode without an AGC Gain
Word”, but whatever adjustment I choose the PCGAIN Pin isn’t logic low all the
time,as it has to be.
As far as I understand the picture has to look like the one on Page 50 of your
AD6654 datasheet, but it is not the same. As I said, on the screen of my logic
generator the PCGAIN Pin is high from time to time.
How can I make sure there is no “AGC GAIN WORD”? What settings do I have to
choose in your software?

Here is what I have tried:
On the Output Port Page of your Software: AGC 1 to 5 Enable (no hack). Port
Settings: Output Gain value for each I & Q output pair (no hack).

Another question is:
For the Time that PCIQ is high, the I Data [15:0] is on the bus. The next PCLK
cycle brings the Q data onto the data bus. My Question is, if Q Data changes
the value before the next PCIQ high level, what data is read out, the value of
Q after the falling edge of PCIQ or the value of Q before the next rising edge
of PCIQ? And changes the Value of I and Q on the bus with the output frequency
that I have chosen?


1. The only way to completely disable the gain word output from the parallel
port is to "disable/bypass" the AGC function for "all" active channels and then
reprogram the AD6654 device. This is accomplished in the eval brd GUI by
de-selecting the "AGC Enable" and "Output gain value for each I/Q pair" options
on the three pages of the "output port" form. Please see attached screen caps
of output port settings GUI. Make sure to disable the AGC for all six channels
0-5, not just 1-5 as you previously noted.

2. The I/Q data output pairs are "registered" together so they always reflect
the same sampled data point. The "Q word" is merely held in queue internally
for output after the related "I word" is shifted out. One way the "Q data word"
might not reflect the same sampled data point as the preceding "I data word"
would be if the processor receiving the PxREQ signal from the AD6654 failed to
pull the PxACK signal high for a sufficient time for the entire I/Q pair to be
shifted out. This would likely cause more obvious handshaking/timing issues
that might allow for dropped/skipped I or Q samples.