AD6645: Spurious noise

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

The problem is related to the A/D converter AD6645 which we use together with
the AD8351 as preamplifier. The diagram of the input circuit can be provided.
The signal is then routed to the downconverter AD6634. We use the filters of
this downconverter as radar matched filters.

We noticed our problem first when we tested the receiver for out-of-band
rejection. The full-scale of the ADC (2.2Vpp) corresponds to an input signal
level of +4.8dBm in our circuit. The input frequency is 60MHz. If the signal
level is increased to 6dBm and the signal is swept up to 68MHz nothing serious
happens. The digital output followed the skirt of the filter which was set up
in the AD6634. Beyond 68MHz an analog antialias filter takes over.

If the signal level was increased to 7dBm the out-of-band signal floor rapidly
rose due to the onset of spurious signals. A plot of the spectrum in the
digital domain can be provided. The 9dBm signal level causes a -1dB compression
of the digital output signal.

We expected to see the rise of harmonic signals once the ADC is driven into
saturation. However we did not find any explanation for the "spurious noise"
which we observed. The problem is quite serious for our application. If we do
not find a solution we have to test a choice of high-speed high-resolution ADCs
for this phenomenon. Can you provide technical information on this subject?

 

For any ADC (not just ADI's) there are only a finite number of digital output
codes between +/-Fullscale. If you input a pure CW sinewave into a high
performance ADC, and perform an FFT analysis on the digital output, you will
typically obtain a very clean spectral plot as shown in the datasheet FFT
figures.  I've also attached -1.0dBFS and -0.5dBFS ADIsimADC 14b ADC model
outputs. This basically holds true as long as your Ain signal remains within
the +/-FS range of the ADC.

As soon as you exceed the ADC's allowable +/-FS range, the output codes start
to rail out at their respective +/-FS static values as shown in d/s table 1.
The clipped ADC digital output starts to look like a clipped sine-wave, or more
like a square-wave. Performing an FFT analysis on a nonsinusoidal clipped sine
or square wave will show that it is rich in odd-order harmonics. Depending on
the relationship between the Ain/Sampling frequencies, "many" of the higher
order harmonics will alias back into the sampled spectrum resulting in a very
"spiky" noise floor as shown in the attached +0.5dBFS ADIsimADC 14b ADC model
output.

The magnitude of the spurious will track the magnitude of the clipping to some
extent, but its not exactly a "linear saturation roll off" as expected by the
customer's comments. All ADC vendors specify performance at a maximum input
level of ~-1.0dBFS to -0.5dBFS to avoid SNR/SFDR perf degradation due to
clipping.

Please note the attached FFT screen caps were obtained using the ADC modeling
features of ADC Analyzer/ADIsimADC. This application and model files are avail
to customers via a free download from our website. Please give the app a try
and let me know if you have any questions about the modeling capabilities.

ADIsimADC Link:
http://www.analog.com/en/design-center/advanced-selection-and-design-tools/inter
active-design-tools/adisimadc.html

Attachments

    Outcomes