Q1)In the AD6643 datasheet, there are two modes of the Interleaved Parallel LVDS
Mode and the Channel Multiplexed (Even/Odd) LVDS Mode available. I would like
to know how to select the modes. But I can not find the dedicated register for
it. Does it control by SPI?Or is there a different part number to clarify them?
2) I find 0x16 is clock phase control bit and 0x14 is output mode bit. Would
you pls help to double check if it is 0x14 but not 0x16?(See attachment)
A1)This was an oversight in the datasheet. To enable the channel multiplexed
(even/odd) mode you need to write reg 0x16 bit 5 to a ‘1’.
2) I understand your concern because of the mode descriptions, but register
0x16 bit 5 is the correct bit to write for the Channel Multiplexed mode.