AD6645: Interfacing to a FPGA

Document created by analog-archivist Employee on Feb 23, 2016
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We intend to use AD6645-105 FADCs running at 100MHz driving into a Xilinx
Virtex II Pro chip. (7 FADCs into one chip). In the AD data sheet there is a
test board diagram which uses a 74LCX574 chip to latch the data output from the
ADC. It shows input and output resistors to match the load on the ADC and
latch. Can I ask Why the LCX574 was chosen and would it be acceptable to use
something like a Texas 74ALVTH16244 or similar buffer chip instead of a latch.
This device has 3pF input capacitance which is lower than the LCX (7pF). We are
concerned about the max min propogation delay spread of the LCX devices in our
application. The Ti device has a spread of only 1 to 3ns max and we can latch
the data in the Virtex device. The resitors could be retained but would they
need to be different values. It seems that the 6645 is very load dependant
since the resistors change between the 65 MHz 6644 device. What is the aim of
the restors in series with the latch input?

 

The purpose of the latches is to isolate the digital outputs of the AD6645 from
the noisy digital logic which follows, and to ensure that the load capacitance
driven by the AD6645 outputs is minimised, all this in order to minimise the
SNR degradation which is caused by the rapidly moving digital outputs inducing
noise onto the die.

The resistors are not really to do any termination, they are more intended to
isolate the AD6645 from the input capacitance of the latch. They are determined
empirically according to the best SNR obtained.

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