AD5422: 3 pin SPI interface

Document created by analog-archivist Employee on Feb 23, 2016
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Regarding AD5422:

Why does its SPI interface not have a chip select pin?

There is a LATCH pin but it doesn't make the system SPI compatible.

Without a chip select pin it impossible to use a device on a SPI bus together
with other SPI devices. (without additional logic)

SCLK and MOSI must be ignored and MISO must go tristate when the device is not
selected. (That is SPI standard)

Questions:

1)
Do you have special devices to make AD5422 fully SPI compatible?

(We could manage it with external logic or a GAL for multiple AD5422 devices
but that has other dissadvantages (in production) we don't want to deal with)

2)
Is there a replacement for the AD5422 that is fully SPI compatible
(including chip select,same features, same accuracy)?

 

The AD5422 will operate on an SPI bus. The LATCH signal can be operated as a CS
signal and used to frame the serial data as shown below.From the point of view
of the AD5422, the rising edge of the LATCH signal is the important event that
latches data into the AD5422, however it does not matter when the LATCH signal
returns low, for SPI compatibility the LATCH signal can be brought low before
the first clock edge and then brought high after the 24th clock edge. There is
no maximum specification on timing parameter t8.

By default the SDO pin (MISO) is tri-state. It will enable if a read is
requested of the AD5422 and tri-state again once the read operation is complete.
When the LATCH signal is brought high the previous 24 bits to be clocked on the
bus will be latched by the AD5422. A write operation tot he AD5422 can be
performed as follows; bring LATCH low, clock 24 bits of data, bring LATCH high.

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