Intrinsic safety - voltage / capacitance minimizing

Document created by analog-archivist Employee on Feb 23, 2016Last modified by MH@CAC on Nov 26, 2016
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A customer request design support for intrinsic safety.


He needs to minimize the capacitance inside the system. As a basis he uses the
Evalboard and an own PCB based on the datasheet:


Question: Which capacitors can be shrinked without loss off function down and
which problems did he have to expect?


For Intrinsic Safety (IS) designs the main challenge is minimizing the maximum
voltage in the system, thereby allowing a wider tolerance on the amount of
capacitance allowable in the design. 
In the case of the AD5421, one consideration is the use of the internal
regulator, which can be programmed to output a regulated 1.8 V to 12 V output
voltage. It’s programmed voltage has a direct impact on the min voltage
necessary at REGIN. If REGOUT is programmed to be < 5.5V, the minimum
acceptable voltage at REGIN is LOOP- + 5.5V. If REGOUT is programmed to be 12
V, REGIN min. is LOOP- + 12.5V.  Assuming max IOUT (24mA) flowing through the
internal 52 Ù resistor, gives 1.25V between COM & LOOP-, therefore, in the case
of REGOUT < 5.5V,  REGIN min is 4.25V with respect to COM, and similarly is
11.25V with respect to COM in the case of REGOUT programmed to 12V.


Typically, in loop-powered transmitter applications, the power supply is
located far from the transmitter device and has a value of 24V. The AD5421 can
be connected directly to the loop power supply and can tolerate a voltage up to
a maximum of 52V.





Alternatively – and more appropriate for IS-conscious designs – a depletion
mode N-channel MOSFET can be connected between the AD5421 and the loop power
supply. The use of this device keeps the voltage drop across the AD5421 at
approximately 12V,  limiting the worst-case on-chip power dissipation to 288mW
(12 V x 24 mA = 288 mW). This 12 V is derived from 11V at the DRIVE pin, plus
the gate-source voltage of the MOSFET. This value DRIVE voltage allows REGOUT
to be programmed to 9V, while also reducing the power dissipation on the AD5421





Using the AD5421 in an IS design limits the amount of charge which can be
stored on the PCB. This, in turn, limits the maximum voltage which can exist on
any pin of any device within in the design, as well as the total capacitance
which can be stored on the pcb. Using the AD5421 as shown above means that the
voltage at the REGIN pin reaches 12V, which places an immediate limit on the
capacitance allowed on the pcb (Q = CV) -  the fault assumption in the case of
IS designs is that ALL pins in an IC can short to eachother.


[In the Figure above the anode of ADR5045, shunt mode Vref, is connected to the
COM pin of AD5421 and the emitter of the top Darlington pair of transistors is
connected to the REGIN pin of AD5421.]


In order to reduce this REGIN voltage, an alternative approach is shown below.
A 5V shunt reference (ADR5045) in series with an npn bipolar darlington
transistor is used to drive the external MOSFET, instead of the AD5421 DRIVE
pin. This architecture splits the power dissipation between the depletion
MOSFET and the darlington bipolar transistor. The minimum voltage at REGIN
becomes approximately 5V (with respect to COM). Thus obeying the previously
calculated min. REGIN of 4.25V with respect to COM when REGOUT < 5.5V. 

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