QOutput voltage range and reduced output swing with greater loading
I am incorporating into a new design the above device. I have
a question on the sink/source capability of the device. Figure
15 of the datasheet shows the output changing with respect to
load, does this just occur near to the two supply rails or will
this occur througout the output voltage range? Or can we source/sink
current from any voltage within the lines on the graph without
the output changing?
ALooking at the way the AD5331 is specified, if you want to have the maximum
output range you should not load the output. Note that in the small print the
DC specifications are tested with the output unloaded while the remaining
specifications are tested with the output connected to ground via a 2k resistor.
The limitation here is the output buffer. An amplifier with a true rail to rail
output stage can swing to within 1mV of the rails if the output current is
less than 1uA. This matches with the AD5331 specifications. However, as soon as
any significant current is sunk or sourced from the amplifiers output, there is
a finite output resistance.
We are now going into the realm of rail to rail output op-amp territory rather
than strictly DAC technology, so please bear with me. What you have at the
output of the AD5331 is basically a rail to rail op-amp configured either as a
unity gain buffer or as a gain of 2 non-inverting amplifier.
When the output voltage is not near either rail, the negative feedback action
of the buffer maintains a very low output resistance. If extra current is
sourced or sunk from the output, the negative feedback loop simply re-adjusts
the drive to the output stage so that the extra current is supplied. Drawing
extra current (within limits) does not cause the output voltage to change
significantly. In this case 0.5 Ohms is the specification given for the AD5331
output impedance at DC.
However, when the output approaches the rails, the internal circuitry begins to
saturate and the FET in the output stage is turned fully on and just looks like
a resistance between the output and the supply rail. Since the FET has no "room
to move" and can't be forced more "on" than it already is, the negative
feedback action described above has no more scope to function and all you see
is a passive resistance to the rail. Drawing current through this resistance
results in a voltage drop across the resistance. You can calculate this output
resistance from figure 15:
R = V/I = 0.3V / 6mA = 50 Ohms.
So the question is:
At what output voltage does the negative feedback cease to be effective causing
the output resistance to rise?
The answer depends on the level of current which is being drawn. There isn't
enough information in the datasheet to say exactly where the boundary might
lie, since the dc parameters are tested unloaded. There's maybe a clue in the
fact that the AD531 linearity is only tested between codes 28 and 1023.
In practise, if you need the output to swing all the way to one or other of the
rails, you refer the load to that rail, causing the current to reduce at the
critical point and allowing the output stage to go all the way to the rail. The
dominant error then will be the offset error of the buffer, which can be
positive or negative and is guaranteed <3% of full scale (150mV @ 5V full
scale). If the offset is negative then the output won't be able to reach the
positive supply rail (Vref = Vdd), if the offset is positive the output won't
be able to reach GND.