AD5318: locked status due to power on

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
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When a slow power up ramp is used, I have problems getting the device to power
up correctly. The only solution is to turn off the power, then turn on again.
The design follows the evaluation board, 0.1uF and 10uF CAP are added to the
Vdd.
The captured power up waveform shows in figure1. We want to confirm whether
AD5318 requires a fast rising-speed of Vdd/Vref during power-up, and any other
suggestions.

 

Looking at the plot, this power up sequence is far from ideal. My opinion is
that the during power up when the part should be completing its power-on-reset
sequence(the part set’s itself up internally) the power is not being applied
properly. The curve of the VDD is non-monotonic and there seems to be noise on
the supply line. A faster Supply ramp is necessary because during a normal
power up somewhere around 2.2V a trigger is hit when the part starts its power
on sequence and it will not complete properly if the supply voltage is not
steadily increasing..
ON page 7 of the AD5318 datasheet, there is an absolute maximum ratings
section, it states that digital input voltage or reference input voltage cannot
go 0.3V above VDD. Please ensure none of the ratings in table 4 are broken.

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