The maximum acceptable clock rise time for the AD5160's reliable operation?

Document created by analog-archivist Employee on Feb 23, 2016
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What is the maximum acceptable clock rise time for reliable operation of the


When using the SPI Interface, it is assumed that the master has strong drivers
so that the input buffers don't have hysteresis. To summarize, we cannot
predict the buffers behaviour when the input signal is between Vil<Vin<Vih.
Furthermore it depends on the temperature and the components deviation (skews).
So, you should guarantee sufficiently fast rising and falling edges and in
other words use external buffers.