FAQ: Why use a PLL architecture that supports High Voltage VCOs?

Document created by aharney Employee on Feb 11, 2010Last modified by AndyR on Jan 31, 2012
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Why use a PLL architecture that supports High Voltage VCOs?




Although Analog Devices makes PLLs such as the ADF4350 which include integrated low-phase-noise VCOs, for very demanding phase noise or higher frequency applications an external VCO is often the only way to go.


For a VCO, the higher its gain (Kv) the higher the VCO noise. So VCO designers will tend to use a low to medium gain (e.g. from 5MHz/V to 70MHz/V) to optimise noise. To get a good useable frequency range a wide tuning range is often required (e.g. from 1V to 12V).


Analog Devices' PLLs typically tune up to about 5V. So an active filter (i.e. Op-Amp) is typically used to interface and level-shift the PLL charge pump output to the higher VCO tuning voltages necessary. ADIsimPLL supports several active filter topologies to help in designing these stages. Active filter stages, however,  tend to add noise and/or spurious content. For a non-inverting stage, generating a low-noise bias voltage is not trivial.


The alternative to active filters is to use a PLL which can directly output charge pump voltages as high as 15V or even 30V. The ADF4113HV and the new ADF4150HV are examples of these.  High voltage PLLs eliminate active filter stage. The use of a standard low-noise passive loop filter means the phase noise can be improved compared to an active filter stage.


Check this Analog Dialogue article "Designing High-Performance Phase-Locked Loops with High-Voltage VCOs" for a more detailed discussion on active loop filter design and  trade-offs.