I2S interface configuration

Document created by analog-archivist Employee on Feb 23, 2016
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In AD1974 datasheet, it mentions AD1974 can support right justified, left
justified, I2S and TDM mode.
But there is no register descriptions on how to enable right justified and left


The BCLK delay register for ADC and DAC should be set according to the
customers needs:

0 BCLK delay = LJ
1 BCLK delay = I2S
8 BCLK delay = RJ for 24-bit audio in 32 BCLK frame
12 BCLK delay = RJ for 20-bit audio in 32 BCLK frame
16 BCLK delay = RJ for 16-bit audio in 32 BCLK frame

TDM mode supports I2S and LJ modes only.