Sample rate lower than 32KHz

Document created by analog-archivist Employee on Feb 23, 2016
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I would like to use the chip below 32KHz sample rate, how should I configure


The default condition would be a 12.288 MHz crystal (48 kHz * 256) and the PLL
using MCLK as its input source. It is possible to set up the AD1938 in a PLL
mode driven from the ALRCLK or DLRCLK port; in this case no connection to MCLKI
or MCLKO is necessary. The internal PLL will run from MCLK sources as low as 32
kHz * 256 = 8.192 MHz. The PLL will not lock to MCLK slower than this
frequency, or to LRCLK slower than 32 kHz. It is possible to shut off the PLL
and drive the MCLK port with (Fs * 512), if the customer would like to slower
than 32 kHz sampling rate.