QI use the AD1938 in slave mode and provide the ALRCLK externally. I would like
to know if I need to configure the PLL INPUT register to set the ALRCLK as the
PLL input, whether I still need to provide the 12.288MHz clock input to the
master clock input pins?
AUsing the AD1939 in LRCLK PLL Mode means that the MCLK of 12.288 MHz is not
needed; this is the whole purpose of the LRCLK PLL mode. It is important that
the Loop Filter values for LRCLK PLL Function are used, instead if the MCLK PLL
values; please find the values in the left diagram of Figure 30.The SPI port is
run independently from the CCLK signal of the 3-wire SPI stream.
The use of the correct Loop Filter values for LRCLK PLL operation is highly
recommended. Operation across all temperature and voltage ranges is not
guaranteed unless the filter is correct. Also, internal jitter will not be
optimized unless the correct values are used.