If the UART is enabled in FIFO mode, the Rx FIFO timeout interrupt occurs if all of the following conditions are satisfied. There is no need for any other register configuration.
- At least one character is in the FIFO
- The most recent character was received more than four continuous character times ago. A character time is the time allotted for 1 START bit, n data bits, 1 PARITY bit, and 1 STOP bit, where n depends on the word length selected with the WLS bits in the line control register (LCR).
- The most recent read of the FIFO has occurred more than four continuous character times before.
The status of the interrupt can be checked in COMIIR - Interrupt ID register (REG_UART0_COMIIR)